AMD-K6-2ESLASH233AMZ datasheet(35/332 Pages) AMD

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Chapter 2

Internal Architecture

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

decodes. The MMX instruction decode generates a RISC86

MMX operation and, optionally, an associated MMX load or

store operation. A 3DNow! instruction decode generates a

RISC86 3DNow! operation and, optionally, an associated load or

store operation. MMX and 3DNow! instructions can be decoded

in either or both of the short decoders.

2.4

Centralized Scheduler

The scheduler is the heart of the AMD-K6-2E processor (see

Figure 5 on page 18). The scheduler contains the logic necessary

to manage out-of-order execution, data forwarding, register

renaming, simultaneous issue and retirement of multiple

RISC86 operations, and speculative execution.

The scheduler’s buffer can hold up to 24 RISC86 operations.

This equates to a maximum of 12 x86 instructions. When

possible, the scheduler can simultaneously issue a RISC86

operation to any available execution unit (store, load, branch,

integer, integer/multimedia, or floating-point). In total, the

scheduler can issue up to six and retire up to four RISC86

operations per clock.

The main advantage of the scheduler and its operation buffer is

the ability to examine an x86 instruction window equal to 12

x86 instructions at one time. This advantage is due to the fact

that the scheduler operates on the RISC86 operations in

parallel and allows the AMD-K6-2E processor to perform

dynamic on-the-fly instruction code scheduling for optimized

execution. Although the scheduler can issue RISC86 operations

for out-of-order execution, it always retires x86 instructions in

order.

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