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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSPIC33F 데이터시트(PDF) 45 Page - Microchip Technology |
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DSPIC33F 데이터시트(HTML) 45 Page - Microchip Technology |
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45 / 80 page  © 2007 Microchip Technology Inc. Preliminary DS70152D-page 45 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 3-4: dsPIC33F/PIC24H DEVICE CONFIGURATION REGISTER MAP Note 1: On the dsPIC33F General Purpose Family devices (dsPIC33FJXXXGPXXX) and PIC24H devices, these bits are reserved (read as ‘1’ and must be programmed as ‘1’). 2: These bits are only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices. In all other devices, they are unimplemented (read as ‘0’). 3: In the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices, these bits are reserved (read as ‘1’ and must be programmed as ‘1’). 3.6.2 PROGRAMMING METHODOLOGY Configuration bits may be programmed a single byte at a time using the PROGC command. This command specifies the configuration data and Configuration register address. When Configuration bits are programmed, any unimplemented bits must be programmed with a ‘0’ and any reserved bits must be programmed with a ‘1’. Twelve PROGC commands are required to program all the Configuration bits. A flowchart for Configuration bit programming is shown in Figure 3-5. 3.6.3 PROGRAMMING VERIFICATION After the Configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful. Verification requires the Configuration bits to be read back and compared against the copy held in the programmer’s buffer. The READC command reads back the programmed Configuration bits and verifies that the programming was successful. Any unimplemented Configuration bits are read-only and read as ‘0’. The reserved bits are read-only and read as ‘1’. 3.6.4 CODEGUARD SECURITY CONFIGURATION BITS The FBS, FSS and FGS Configuration registers are special Configuration registers that control the size and level of code protection for the Boot Segment, Secure Segment and General Segment, respectively. For each segment, two main forms of code protection are provided. One form prevents code memory from being written (write protection), while the other prevents code memory from being read (read protection). BWRP, SWRP and GWRP bits control write protection and BSS<2:0>, SSS<2:0> and GSS<1:0> bits controls read protection. The Chip Erase ERASEB command sets all the code protection bits to ‘1’, which allows the device to be programmed. When write protection is enabled, any programming operation to code memory will fail. When read protec- tion is enabled, any read from code memory will cause a ‘0x0’ to be read, regardless of the actual contents of code memory. Since the programming executive always verifies what it programs, attempting to program code memory with read protection enabled will also result in failure. It is imperative that all code protection bits are ‘1’ while the device is being programmed and verified. Only after the device is programmed and verified should any of the above bits be programmed to ‘0’. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0xF80000 FBS RBS<1:0>(3) — BSS<2:0> BWRP 0xF80002 FSS RSS<1:0>(3) — SSS<2:0>(3) SWRP(3) 0xF80004 FGS — GSS<1:0> GWRP 0xF80006 FOSCSEL IESO — TEMP — FNOSC<2:0> 0xF80008 FOSC FCKSM<1:0> IOL1WAY(2) — OSCIOFNC POSCMD<1:0> 0xF8000A FWDT FWDTEN WINDIS - WDTPRE WDTPOST<3:0> 0xF8000C FPOR PWMPIN(1) HPOL(1) LPOL(1) ALTI2C(2) —FPWRT<2:0> 0xF8000E FICD BKBUG COE JTAGEN — ICS<1:0> 0xF80010 FUID0 User Unit ID Byte 0 0xF80012 FUID1 User Unit ID Byte 1 0xF80014 FUID2 User Unit ID Byte 2 0xF80016 FUID3 User Unit ID Byte 3 Note: If the General Code Segment Code- Protect bit (GCP) is programmed to ‘0’, code memory is code-protected and can not be read. Code memory must be verified before enabling read protec- tion. See Section 3.6.4 “CodeGuard Security Configuration Bits” for more information about code-protect Configura- tion bits. |
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