DSPIC33F datasheet(58/80 Pages) MICROCHIP

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dsPIC33F/PIC24H PROGRAMMING SPECIFICATION

DS70152D-page 58

Preliminary

TABLE 5-3:

NVMCON WRITE

OPERATIONS

5.4.2

STARTING AND STOPPING A

PROGRAMMING CYCLE

The WR bit (NVMCON<15>) is used to start an erase or

write cycle. Setting the WR bit initiates the programming

cycle.

All erase and write cycles are self-timed. The WR bit

should be polled to determine if the erase or write cycle

has been completed. Starting a programming cycle is

performed as follows:

BSET

NVMCON, #WR

5.5

Erasing Program Memory

The procedure for erasing program memory (all of code

memory, data memory, executive memory and code-

protect bits) consists of setting NVMCON to 0x404F

and then executing the programming cycle. For seg-

ment erase operations, the NVMCON value should be

modified suitably, according to Table 5-2.

Figure 5-5 shows the ICSP programming process for

Bulk Erasing program memory. This process includes

the ICSP command code, which must be transmitted

(for each instruction) Least Significant bit first, using the

PGC and PGD pins (see Figure 5-2).

FIGURE 5-5:

BULK ERASE FLOW

If a Segment Erase operation is required, Step 3 must

be modified with the appropriate NVMCON value as

per Table 5-2.

The ability to individually erase various segments is a

critical component of the CodeGuard™ Security fea-

tures on dsPIC33F/PIC24H devices. An individual

code segment may be erased without affecting other

segments. In addition, the Configuration register corre-

sponding to the erased code segment also gets

erased. For example, the user might want to erase the

code in the General Segment without erasing a Boot

Loader located in Boot Segment.

The Secure Segment Erase command is used to erase

the Secure Segment and the FSS Configuration regis-

ter. The General Segment Erase command is used to

erase the General Segment and the FGS Configuration

Segment or Secure Segment has been enabled.

Before performing any segment erase operation, the

programmer must first determine if the dsPIC33F/

PIC24H device has defined a Boot Segment or Secure

Segment, and ensure that a segment does not get

overwritten by operations on any other segment. Also,

a Bulk Erase should not be performed if a Boot

Segment or Secure Segment has been defined.

The BSS bit field in the FBS configuration register can

be read to determine whether a Boot Segment has

been defined. If a Boot Segment has already been

defined (and probably already been programmed), the

user must be warned about this fact. Similarly, the SSS

bit field in the FSS configuration register can be read to

determine whether a Secure Segment has been

defined. If a Secure Segment has already been defined

(and probably already been programmed), the user

must be warned about this fact.

A Bulk Erase operation is the recommended mecha-

nism to allow a user to overwrite the Boot Segment (if

one chooses to do so).

In general, the segments and CodeGuard Security-

related configuration registers should be programmed

in the following order:

• FBS and Boot Segment

• FSS and Secure Segment

• FGS and General Segment

NVMCON

Value

Write Operation

0x4001

Program 1 row (64 instruction words)

of code memory or executive memory.

0x4000

Write a Configuration register byte.

0x4003

Program a code memory word.

Note:

Program memory must be erased before

writing any data to program memory.

Start

Done

Set the WR bit to Initiate Erase

Write 0x404F to NVMCON SFR

Delay P11 + P10 Time

Note 1: The Boot Segment and FBS Configura-

tion register can only be erased using a

Bulk Erase.

2: A Secure Segment Erase operation also

erases the General Segment and FGS

Configuration register. This is true even if

Secure Segment is present on a device

but not enabled.

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