DSPIC33F datasheet(56/80 Pages) MICROCHIP

56 / 80 page

dsPIC33F/PIC24H PROGRAMMING SPECIFICATION

DS70152D-page 56

Preliminary

5.2.1

SIX SERIAL INSTRUCTION

EXECUTION

The SIX control code allows execution of dsPIC33F/

PIC24H Programming Specification assembly instruc-

tions. When the SIX code is received, the CPU is sus-

pended for 24 clock cycles, as the instruction is then

clocked into the internal buffer. Once the instruction is

shifted in, the state machine allows it to be executed over

the next four clock cycles. While the received instruction

is executed, the state machine simultaneously shifts in

the next 4-bit command (see Figure 5-2).

5.2.2

REGOUT SERIAL INSTRUCTION

EXECUTION

The REGOUT control code allows for data to be

extracted from the device in ICSP mode. It is used to

clock the contents of the VISI register out of the device

over the PGD pin. After the REGOUT control code is

received, the CPU is held Idle for 8 cycles. After these

eight cycles, an additional 16 cycles are required to clock

the data out (see Figure 5-3).

The REGOUT code is unique because the PGD pin is

an input when the control code is transmitted to the

device. However, after the control code is processed,

the PGD pin becomes an output as the VISI register is

shifted out.

FIGURE 5-2:

SIX SERIAL EXECUTION

FIGURE 5-3:

REGOUT SERIAL EXECUTION

Note 1: Coming out of Reset, the first 4-bit control

code is always forced to SIX and a forced

NOP

instruction is executed by the CPU.

Five additional PGC clocks are needed

on start-up, thereby resulting in a 9-bit

SIX command instead of the normal 4-bit

SIX command. After the forced SIX is

clocked in, ICSP operation resumes as

normal (the next 24 clock cycles load the

first instruction word to the CPU).

2: TBLRDH, TBLRDL, TBLWTH and TBLWTL

instructions must be followed by a NOP

instruction.

Note:

Data is transmitted on the falling edge and

latched on the rising edge of PGC. For all

data transmissions, the Least Significant

bit (LSb) is transmitted first.

23 24

PGC

P4a

PGD

24-Bit Instruction Fetch

Execute 24-Bit Instruction,

Execute PC – 1,

Fetch SIX Control Code

Fetch Next Control Code

19 20

LSB X

X MSB

PGD = Input

P1B

P1A

Only for

Program

Memory Entry

PGC

PGD

PGD = Input

Execute Previous Instruction,

CPU Held in Idle

Shift Out VISI Register<15:0>

PGD = Output

P4a

15 16

No Execution Takes Place,

Fetch Next Control Code

PGD = Input

MSb

LSb

...

Fetch REGOUT Control Code

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