DSPIC33F datasheet(57/80 Pages) MICROCHIP

57 / 80 page

Preliminary

DS70152D-page 57

dsPIC33F/PIC24H PROGRAMMING SPECIFICATION

5.3

Entering ICSP Mode

As shown in Figure 5-4, entering ICSP Program/Verify

mode requires three steps:

MCLR is briefly driven high then low.

A 32-bit key sequence is clocked into PGD.

MCLR is then driven high within a specified

period of time and held.

The programming voltage applied to MCLR is VIH,

which is essentially VDD in the case of dsPIC33F/

PIC24H devices. There is no minimum time require-

ment for holding at VIH. After VIH is removed, an inter-

val of at least P18 must elapse before presenting the

key sequence on PGD.

The key sequence is a specific 32-bit pattern,

‘0100 1101 0100 0011 0100 1000 0101 0001’

(more easily remembered as 0x4D434851 in hexa-

decimal). The device will enter Program/Verify mode only

if the sequence is valid. The Most Significant bit (MSb) of

the most significant nibble must be shifted in first.

Once the key sequence is complete, VIH must be

applied to MCLR and held at that level for as long as

Program/Verify mode is to be maintained. An interval of

at least time P19 and P7 must elapse before presenting

data on PGD. Signals appearing on PGD before P7

has elapsed will not be interpreted as valid.

On successful entry, the program memory can be

accessed and programmed in serial fashion. While

in ICSP mode, all unused I/Os are placed in the

high-impedance state.

FIGURE 5-4:

ENTERING ICSP™ MODE

5.4

Flash Memory Programming in

ICSP Mode

5.4.1

PROGRAMMING OPERATIONS

Flash memory write and erase operations are controlled

by the NVMCON register. Programming is performed by

setting NVMCON to select the type of erase operation

(Table 5-2) or write operation (Table 5-3) and initiating

the programming by setting the WR control bit

(NVMCON<15>).

In ICSP mode, all programming operations are self-

timed. There is an internal delay between the user set-

ting the WR control bit and the automatic clearing of the

WR control bit when the programming operation is

complete. Please refer to Section TABLE 8-1: “AC/

DC Characteristics and Timing Requirements” for

information about the delays associated with various

programming operations.

TABLE 5-2:

NVMCON ERASE

OPERATIONS

MCLR

PGD

PGC

VDD

P14

b31

b30

b29

b28

b27

...

Program/Verify Entry Code = 0x4D434851

P1A

P1B

P18

P19

001

000

VIH

NVMCON

Value

Erase Operation

0x404F

Erase all code memory, executive memory

and Configuration registers (does not

erase Unit ID or Device ID registers).

0x404D

Erase General Segment and FGS

Configuration register.

0x404C

Erase Secure Segment and FSS

Configuration register. This operation will

also erase the General Segment and FGS

Configuration register.

0x4042

Erase a page of code memory or

executive memory.

0x4040

Erase a Configuration register byte.

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