WM8804 datasheet(50/66 Pages) WOLFSON

50 / 66 page

WM8804

Production Data

PD Rev 4.1 September 2007

AUDIO INTERFACE CONTROL

The register bits controlling the audio interface are summarised below. Note that dynamically

changing the audio data format may cause erroneous operation, and hence is not recommended.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

WITHFLAG

‘With Flags’ Mode Select

0: ‘With Flags’ Mode disabled (see Note 3)

1: ‘With Flags’ Mode enabled

R29

SPDIFRX1

1Dh

WL_MASK

S/PDIF Receiver Word Length Truncation

Mask

0 = disabled, data word is truncated as

described in Table 44 S/PDIF Receiver

Channel Status Register 5

1 = enabled, data word is not truncated.

1:0

AIFTX_FMT[1:0]

Audio Data Format Select

11: DSP mode

10: I2S mode

01: Left justified mode

00: Right justified mode

3:2

AIFTX_WL[1:0]

Audio Data Word Length

11: 24 bits (see notes 1/2/3/6)

10: 24 bits (see notes 1/2/3/6)

01: 20 bits

00: 16 bits

AIFTX_BCP

BCLK invert (for master and slave modes)

0 = BCLK not inverted

1 = BCLK inverted

R27

AIFTX

1Bh

AIFTX_LRP

Right, left and I2S modes – LRCLK polarity and

DSP mode select

1 = invert LRCLK polarity / DSP Mode B

0 = normal LRCLK polarity / DSP Mode A

1:0

AIFRX_FMT[1:0]

Audio Data Format Select

11: DSP mode

10: I

2S mode

01: Left justified mode

00: Right justified mode

3:2

AIFRX_WL[1:0]

Audio Data Word Length

11: 24 bits (see note 1/2/3/6)

10: 24 bits

01: 20 bits

00: 16 bits

AIFRX_BCP

BCLK Invert (for master and slave modes)

0 = BCLK not inverted

1 = BCLK inverted

See Note 4

R28

AIFRX

1Ch

AIFRX_LRP

Right, left and I

2S modes – LRCLK polarity and

DSP mode select

1 = invert LRCLK polarity / DSP Mode B

0 = normal LRCLK polarity / DSP Mode A

See Note 5

Table 56 Audio Interface Control

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