WM8804 datasheet(7/66 Pages) WOLFSON

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Production Data

WM8804

PD Rev 4.1 September 2007

MASTER CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 Slave Mode MCLK Timing Requirements

Test Conditions

PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information – Slave Mode

MCLK System clock cycle time

tMCLKY

MCLK System clock pulse width high

tMCLKH

MCLK System clock pulse width low

tMLCKL

MCLK Duty cycle

40:60

60:40

Table 1 Master Clock Timing Requirements

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

DOUT

LRCLK

DIN

DDA

DHT

DST

Figure 2 Digital Audio Data Timing – Master Mode

Test Conditions

PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRCLK propagation delay from

BCLK falling edge

tDL

DOUT propagation delay from

BCLK falling edge

tDDA

DIN setup time to BCLK rising

edge

tDST

DIN hold time from BCLK rising

edge

tDHT

Table 2 Digital Audio Data Timing – Master Mode

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