| 전자부품 데이터시트 검색엔진 |
|
WM8804 데이터시트(PDF) 8 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8804 데이터시트(HTML) 8 Page - Wolfson Microelectronics plc |
|
8 / 66 page ![]() WM8804 Production Data w PD Rev 4.1 September 2007 8 DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK LRCLK t BCH t BCL t BCY DIN DOUT t LRSU t DS t LRH t DH t DD Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DIN set-up time to BCLK rising edge tDS 10 ns DIN hold time from BCLK rising edge tDH 10 ns DOUT propagation delay from BCLK falling edge tDD 0 10 ns Table 3 Digital Audio Data Timing – Slave Mode |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |