UPSD3422 datasheet(52/293 Pages) STMICROELECTRONICS

52 / 293 page

Interrupt system

uPSD34xx

52/293

Interrupt system

The uPSD34xx has an 12-source, two priority level interrupt structure summarized in

Table 16.

Firmware may assign each interrupt source either high or low priority by writing to bits in the

SFRs named, IP and IPA, shown in Table 16. An interrupt will be serviced as long as an

interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or

higher priority is being serviced, the new interrupt will wait until it is finished before being

serviced. If a lower priority interrupt is being serviced, it will be stopped and the new

interrupt is serviced. When the new interrupt is finished, the lower priority interrupt that was

stopped will be completed. If new interrupt requests are of the same priority level and are

received simultaneously, an internal polling sequence determines which request is selected

for service. Thus, within each of the two priority levels, there is a second priority structure

determined by the polling sequence.

Firmware may individually enable or disable interrupt sources by writing to bits in the SFRs

named, IE and IEA, shown in Table 16 on page 53. The SFR named IE contains a global

disable bit (EA), which can be cleared to disable all 12 interrupts at once, as shown in

Table 17 on page 56. Figure 13 on page 54 illustrates the interrupt priority, polling, and

enabling process.

Each interrupt source has at least one interrupt flag that indicates whether or not an

interrupt is pending. These flags reside in bits of various SFRs shown in Table 16 on

page 53.

All of the interrupt flags are latched into the interrupt control system at the beginning of each

MCU machine cycle, and they are polled at the beginning of the following machine cycle. If

polling determines one of the flags was set, the interrupt control system automatically

generates an LCALL to the user’s Interrupt Service Routine (ISR) firmware stored in

program memory at the appropriate vector address.

●

The specific vector address for each of the interrupt sources are listed in Table 16 on

page 53. However, this LCALL jump may be blocked by any of the following conditions:

●

An interrupt of equal or higher priority is already in progress

●

The current machine cycle is not the final cycle in the execution of the instruction in

progress

●

The current instruction involves a write to any of the SFRs: IE, IEA, IP, or IPA

●

The current instruction is an RETI

Note:

Interrupt flags are polled based on a sample taken in the previous MCU machine cycle. If an

interrupt flag is active in one cycle but is denied serviced due to the conditions above, and

then later it is not active when the conditions above are finally satisfied, the previously

denied interrupt will not be serviced. This means that active interrupts are not remembered.

Every poling cycle is new.

Assuming all of the listed conditions are satisfied, the MCU executes the hardware

generated LCALL to the appropriate ISR. This LCALL pushes the contents of the PC onto

the stack (but it does not save the PSW) and loads the PC with the appropriate interrupt

vector address. Program execution then jumps to the ISR at the vector address.

Execution precedes in the ISR. It may be necessary for the ISR firmware to clear the

pending interrupt flag for some interrupt sources, because not all interrupt flags are

automatically cleared by hardware when the ISR is called, as shown in Table 16 on page 53.

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