UPSD3422 datasheet(44/293 Pages) STMICROELECTRONICS

44 / 293 page

uPSD34xx instruction set summary

uPSD34xx

44/293

Table 8.

Data transfer instruction set

Note:

All mnemonics copyrighted ©Intel Corporation 1980.

This instruction is not supported by uPSD34xx. See Section 9.6: External Indirect

Addressing on page 39

Mnemonic(1) and Use

Description

Length/Cycles

MOV

A, Rn

Move register to ACC

1 byte/1 cycle

MOV

A, direct

Move direct byte to ACC

2 byte/1 cycle

MOV

A, @Ri

Move indirect SRAM to ACC

1 byte/1 cycle

MOV

A, #data

Move immediate data to ACC

2 byte/1 cycle

MOV

Rn, A

Move ACC to register

1 byte/1 cycle

MOV

Rn, direct

Move direct byte to register

2 byte/2 cycle

MOV

Rn, #data

Move immediate data to register

2 byte/1 cycle

MOV

direct, A

Move ACC to direct byte

2 byte/1 cycle

MOV

direct, Rn

Move register to direct byte

2 byte/2 cycle

MOV

direct, direct

Move direct byte to direct

3 byte/2 cycle

MOV

direct, @Ri

Move indirect SRAM to direct byte

2 byte/2 cycle

MOV

direct, #data

Move immediate data to direct byte

3 byte/2 cycle

MOV

@Ri, A

Move ACC to indirect SRAM

1 byte/1 cycle

MOV

@Ri, direct

Move direct byte to indirect SRAM

2 byte/2 cycle

MOV

@Ri, #data

Move immediate data to indirect SRAM

2 byte/1 cycle

MOV

DPTR,

#data16

Load Data Pointer with 16-bit constant

3 byte/2 cycle

MOVC

A, @A+DPTR Move code byte relative to DPTR to ACC

1 byte/2 cycle

MOVC

A, @A+PC

Move code byte relative to PC to ACC

1 byte/2 cycle

MOVX

A, @Ri (2)

Move XDATA (8-bit addr) to ACC

1 byte/2 cycle

MOVX

A, @DPTR

Move XDATA (16-bit addr) to ACC

1 byte/2 cycle

MOVX

@Ri, A (2)

Move ACC to XDATA (8-bit addr)

1 byte/2 cycle

MOVX

@DPTR, A

Move ACC to XDATA (16-bit addr)

1 byte/2 cycle

XCH

A, Rn

Exchange register with ACC

1 byte/1 cycle

PUSH

direct

Push direct byte onto stack

2 byte/2 cycle

POP

direct

Pop direct byte from stack

2 byte/2 cycle

XCH

A, direct

Exchange direct byte with ACC

2 byte/1 cycle

XCH

A, @Ri

Exchange indirect SRAM with ACC

1 byte/1 cycle

XCHD

A, @Ri

Exchange low-order digit indirect SRAM with

ACC

1 byte/1 cycle

UPSD3422 데이터시트(PDF) 44 Page - STMicroelectronics

UPSD3422 데이터시트(HTML) 44 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL