UPSD3422 datasheet(43/293 Pages) STMICROELECTRONICS

43 / 293 page

uPSD34xx

uPSD34xx instruction set summary

43/293

Note:

All mnemonics copyrighted ©Intel Corporation 1980.

Table 7.

Logical instruction set

Note:

All mnemonics copyrighted ©Intel Corporation 1980.

INC

DPTR

Increment Data Pointer

1 byte/2 cycle

MUL

Multiply ACC and B

1 byte/4 cycle

DIV

Divide ACC by B

1 byte/4 cycle

Decimal adjust ACC

1 byte/1 cycle

Mnemonic(1) and Use

Description

Length/Cycles

Mnemonic(1) and Use

Description

Length/Cycles

Logical Instructions

ANL

A, Rn

AND register to ACC

1 byte/1 cycle

ANL

A, direct

AND direct byte to ACC

2 byte/1 cycle

ANL

A, @Ri

AND indirect SRAM to ACC

1 byte/1 cycle

ANL

A, #data

AND immediate data to ACC

2 byte/1 cycle

ANL

direct, A

AND ACC to direct byte

2 byte/1 cycle

ANL

direct, #data

AND immediate data to direct byte

3 byte/2 cycle

ORL

A, Rn

OR register to ACC

1 byte/1 cycle

ORL

A, direct

OR direct byte to ACC

2 byte/1 cycle

ORL

A, @Ri

OR indirect SRAM to ACC

1 byte/1 cycle

ORL

A, #data

OR immediate data to ACC

2 byte/1 cycle

ORL

direct, A

OR ACC to direct byte

2 byte/1 cycle

ORL

direct, #data

OR immediate data to direct byte

3 byte/2 cycle

SWAP

Swap nibbles within the ACC

1 byte/1 cycle

XRL

A, Rn

Exclusive-OR register to ACC

1 byte/1 cycle

XRL

A, direct

Exclusive-OR direct byte to ACC

2 byte/1 cycle

XRL

A, @Ri

Exclusive-OR indirect SRAM to ACC

1 byte/1 cycle

XRL

A, #data

Exclusive-OR immediate data to ACC

2 byte/1 cycle

XRL

direct, A

Exclusive-OR ACC to direct byte

2 byte/1 cycle

XRL

direct, #data

Exclusive-OR immediate data to direct byte

3 byte/2 cycle

CLR

Clear ACC

1 byte/1 cycle

CPL

Compliment ACC

1 byte/1 cycle

Rotate ACC left

1 byte/1 cycle

RLC

Rotate ACC left through the carry

1 byte/1 cycle

Rotate ACC right

1 byte/1 cycle

RRC

Rotate ACC right through the carry

1 byte/1 cycle

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