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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPSD3422 데이터시트(PDF) 71 Page - STMicroelectronics |
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UPSD3422 데이터시트(HTML) 71 Page - STMicroelectronics |
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71 / 293 page  uPSD34xx I/O ports of mcu module 71/293 CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All other types of reads to port SFRs will read the actual pin logic level and not the port latch. This is consistent with 8051 architecture. Figure 16. MCU module port pin function routing Figure 17. MCU I/O cell block diagram for port 1 8 P3 P1 P4 M C U A D GPIO (8) UART0 (2) TIMER0/1 (4) I 2 C (2) GPIO (8) GPIO (8) TIMER2 (2) UART1 (2) SPI (4) ADC (8) PCA (8) 8032 MCU CORE Low Addr & Data[7:0] 8 Hi Address [15:8] (Available on PSD Module Pins) MCU Module 8 On 80-pin Devices Only Ports C N T L RD, WR, PSEN, ALE 4 SFR 8 8 SFR SFR SFR SFR SFR AI09199b P1.X Pin Analog_Alt_Func_En Analog_Pin_In Q D PRE SFR P1.X Latch 8032 Data Bus Bit GPIO P1.X SFR Write Latch MCU_Reset P1.X SFR Read Latch (for R-M-W instructions) P1.X SFR Read Pin Select_Alternate_Func Digital_Pin_Data_In IN 1 IN 0 Y MUX VCC VCC VCC SEL WEAK PULL-UP, B STONGER PULL-UP, A LOW SIDE HIGH SIDE DELAY, 1 MCU_CLK DELAY, 1 MCU_CLK Q Digital_Alt_Func_Data_Out AI09600 |
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