UPSD3422 datasheet(112/293 Pages) STMICROELECTRONICS

112 / 293 page

IrDA interface

uPSD34xx

112/293

The UART1 serial channel can operate in one of four different modes as shown in Table 46

on page 100 in Section 21: Serial UART interfaces on page 99. However, when UART1 is

used for IrDA communication, UART1 must operate in Mode 1 only, to be compatible with

IrDA protocol up to 115.2k bps. The IrDA interface will support baud rates generated from

Timer 1 or Timer 2, just like standard UART serial communication, but with one restriction.

The transmit baud rate and receive baud rate must be the same (cannot be different rates as

is allowed by standard UART communications).

The IrDA Interface is disabled after a reset and is enabled by setting the IRDAEN Bit in the

SFR named IRDACON (Table 50 on page 112). When IrDA is disabled, the UART1's RxD

and TxD signals will bypass the internal IrDA logic and instead they are routed directly to the

pins RxD1 and TxD1 respectively. When IrDA is enabled, the IrDA pulse shaping logic is

active and resides between UART1 and the pins RxD1 and TxD1 as shown in Figure 39 on

page 111.

22.1

Baud rate selection

The IrDA standard only supports 2.4, 9.6, 19.2, and 115.2kbps. Table 52 on page 113

informs the IrDA Interface of the baud rate of UART#1 so that it can perform pulse

modulation properly. It may not be necessary to implement the BR[3:0] bits in the IRDACON

Table 50.

IRDACON register bit definition (SFR CEh, reset value 0Fh)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

IRDAEN

PULSE

CDIV4

CDIV3

CDIV2

CDIV1

CDIV0

Bit

Symbol

R/W

Definition

–

Reserved

IRDAEN

IrDA Enable

0 = IrDA Interface is disabled

1 = IrDA is enabled, UART1 outputs are disconnected from

Port 1 (or Port 4)

5PULSE

IrDA Pulse Modulation Select

0 = 1.627µs

1 = 3/16 bit time pulses

4-0

CDIV[4:0]

Specify Clock Divider (see Table 53 on page 114)

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