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UPSD3422 데이터시트(PDF) 142 Page - STMicroelectronics |
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UPSD3422 데이터시트(HTML) 142 Page - STMicroelectronics |
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142 / 293 page ![]() SPI (synchronous peripheral interface) uPSD34xx 142/293 Table 66. SPISTAT: SPI interface status register (SFR D3h, reset value 02h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – BUSY TEISF RORISF TISF RISF Bit Symbol R/W Definition 7-5 – – Reserved 4BUSY R SPI Busy 0 = Transmit or Receive is completed 1 = Transmit or Receive is in process 3 TEISF R Transmission End Interrupt Source flag 0 = Automatically resets to '0' when firmware reads this register 1 = Automatically sets to '1' when transmission end occurs 2 RORISF R Receive Overrun Interrupt Source flag 0 = Automatically resets to '0' when firmware reads this register 1 = Automatically sets to '1' when receive overrun occurs 1TISF R Transfer Interrupt Source flag 0 = Automatically resets to '0' when SPITDR is full (just after the SPITDR is written) 1 = Automatically sets to '1' when SPITDR is empty (just after byte loads from SPITDR into SPI shift register) 0RISF R Receive Interrupt Source flag 0 = Automatically resets to '0' when SPIRDR is empty (after the SPIRDR is read) 1 = Automatically sets to '1' when SPIRDR is full |
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