UPSD3422 datasheet(173/293 Pages) STMICROELECTRONICS

173 / 293 page

uPSD34xx

Analog-to-digital convertor (ADC)

173/293

Table 89.

ACON register (SFR 97h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AINTF

AINTEN

ADEN

ADS2

ADS1

ADS0

ADST

ADSF

Bit

Symbol

Function

7AINTF

ADC Interrupt flag. This bit must be cleared with software.

0 = No interrupt request

1 = The AINTF flag is set when ADSF goes from '0' to '1.' Interrupts CPU when

both AINTF and AINTEN are set to '1.'

6AINTEN

ADC Interrupt Enable

0 = ADC interrupt is disabled

1 = ADC interrupt is enabled

5ADEN

ADC Enable Bit

0 = ADC shut off and consumes no operating current

1 = Enable ADC. After ADC is enabled, 16ms of calibration is needed before

ADST Bit is set.

4.. 2

ADS2.. 0

Analog channel Select

000 Select channel 0 (P1.0)

001 Select channel 0 (P1.1)

010 Select channel 0 (P1.2)

011 Select channel 0 (P1.3)

101 Select channel 0 (P1.5)

110 Select channel 0 (P1.6)

111 Select channel 0 (P1.7)

1ADST

ADC Start Bit

0 = Force to zero

1 = Start ADC, then after one cycle, the bit is cleared to '0.'

0ADSF

ADC Status Bit

0 = ADC conversion is not completed

1 = ADC conversion is completed. The bit can also be cleared with software.

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