UPSD3422 datasheet(183/293 Pages) STMICROELECTRONICS

183 / 293 page

uPSD34xx

Programmable counter array (PCA) with PWM

183/293

Table 98.

PCA status register PCASTA (SFR 0A5h, reset value 00h)

27.13

TCM interrupts

There are 8 TCM interrupts: 6 match or capture interrupts and two counter overflow

interrupts. The 8 interrupts are “ORed” as one PCA interrupt to the CPU.

By the nature of PCA application, it is unlikely that many of the interrupts occur

simultaneously. If they do, the CPU has to read the interrupt flags and determine which one

to serve. The software has to clear the interrupt flag in the Status Register after serving the

interrupt.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OVF1

INTF5

INTF4

INTF3

OVF0

INTF2

INTF1

INTF0

Bit

Symbol

Function

7OFV1

PCA1 Counter OverFlow flag

Set by hardware when the counter rolls over. OVF1 flags an interrupt if Bit

EOVFI in PCACON1 is set. OVF1 may be set with either hardware or

software but can only be cleared with software.

6INTF5

TCM5 Interrupt flag

Set by hardware when a match or capture event occurs.

Must be clear with software.

5INTF4

TCM4 Interrupt flag

Set by hardware when a match or capture event occurs.

Must be clear with software.

4INTF3

TCM3 Interrupt flag

Set by hardware when a match or capture event occurs.

Must be clear with software.

3OVF0

PCA0 Counter OverFlow flag

Set by hardware when the counter rolls over. OVF0 flags an interrupt if Bit

EOVFI in PCACON0 is set. OVF1 may be set with either hardware or

software but can only be cleared with software.

2INTF2

TCM2 Interrupt flag

Set by hardware when a match or capture event occurs.

Must be clear with software.

1INTF1

TCM1 Interrupt flag

Set by hardware when a match or capture event occurs.

Must be clear with software.

0INTF0

TCM0 Interrupt flag

Set by hardware when a match or capture event occurs.

Must be clear with software.

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