TMP93CS41 datasheet(128/248 Pages) TOSHIBA

128 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-126

Example: To output the following PWM waves to the TO2 pin using PWM0 at

= 20 MHz

Clock condition

System clock:

High frequency (fc)

Clock gear:

1 (fc)

Prescaler clock: fFPH

To implement 25.4

µs as the PWM cycle regulated by φP1 = 0.2 µs (at fc = 20 MHz)

− 1 = 25.4 µs ÷ 0.2 µs = 127.

Consequently, set n to 7.

Since the low level cycle

= 12 µs; for φP1 = 0.2 µs

3CH

= 12 µs ÷ 0.2 = 60

set the 3CH in TREG2.

TRUN

← − X − − − 0 − −

Stops PWM0 and clears it.

P0MOD

← − 0 0 0 0 0 0 1

Sets PWM (2

− 1) mode, input clock φP1, overflow

interrupt, and disables double buffer.

TREG2

← 0 0 1 1 1 1 0 0

Writes 3CH.

P0MOD

← − 1 0 0 0 0 0 1

Enables double buffer.

PFFCR

← − − − − 0 1 1 0

Sets TFF2 and the mode in which TFF2 is set by compare

and match, and cleared by overflow.

P7CR

← X X X X − 1 − −

P7FC

← X X X X − 1 − X

Sets P72 as TO2 pin.

TRUN

← 1 X − − − 1 − −

Starts PWM0 counting.

X: Don’t care, −: No change

µs

25.4

µs

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