TMP93CS41 datasheet(151/248 Pages) TOSHIBA

151 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-149

Setting example: To output a 2 ms one-shot pulse to the external trigger pulse to TI4 pin,

with 3 ms delay

Clock condition

System clock:

High frequency (fc)

Clock gear:

1 (fc)

Prescaler clock:

fFPH

Main setting

Keep counting (Free running)

Count with

φT1.

T4MOD

← − − 1 01 00 1

Load the up counter value into CAP1 at the rising edge of

TI4 pin input.

T4FFCR

← 1 1 0 0 0 0 1 0

Clear TFF4 to zero.

Disable TFF4 inversion.

P8CR

← − − − − − 1 − −

P8FC

← X − X X − 1X X

Select P82 as the TO4 pin.

INTE45

← − − − − 1 1 0 0

Enable INT4, and disable INTTR4 and INTTR5.

INTET54

← 1 0 0 0 1 0 0 0

TRUN

← 1 X − 1 − − − −

Start timer 4.

Setting of INT4

TREG4

←

CAP1

+ 3 ms/φT1

TREG5

←

TREG4

+ 2 ms/φT1

T4FFCR

← − − − − 11 − −

Enable TFF4 inversion when the up counter value

matches TREG4 or TREG5.

INTET54

← 1 1 0

− − − −

Enable INTTR5.

Setting of INTTR5

T4FFCR

← − − − −

− −

Disable TFF4 inversion when the up counter value

matches TREG4 or TREG5.

INTET54

← 1 0 0 0

−

− −

Disable INTTR5.

X: Don’t care, −: No change

When a delay time is unnecessary, invert the timer flip-flop TFF4 by loading the up

counter value into capture register 1 (CAP1). Then set TREG5 to the CAP1 value (c) plus

the one-shot pulse width (p) when an INT4 interrupt occurs. The TFF4 inversion should be

enabled when the up counter (UC4) value matches TREG5, and disabled when generating

the interrupt INTTR5.

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