TMP93CS41 datasheet(160/248 Pages) TOSHIBA

160 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-158

Bit symbol

QCU

PG1T

PG0T

DB6EN

DB4EN

Read/Write

R/W

After reset

Double buffer

0: Disable

1: Enable

Function

Watchdog/

warm-up

timer

control

PG1 shift

trigger

0: 8-bit

timer

trigger

(Timers

0 and 1)

1: 16-bit

timer

trigger

(Timer 5)

PG0 shift

trigger

0: 8-bit

timer

trigger

(Timers

0 and 1)

1: 16-bit

timer

trigger

(Timer 4)

Double

buffer for

TREG6

Double

buffer for

TREG4

Note 1: When the 7-stage binary counter is not used as a warm-up timer, a stable clock must be input from an external circuit.

Note 2: T45CR<bit6:4> are always 1.

Figure 3.10.6 16-Bit Timer Trigger Control Register (T45CR)

T45CR

(003AH)

8-bit timer trigger (Timers 0 and 1)

16-bit timer trigger (Timer 4)

Selecting PG0 shift trigger

Disable

Enable

Double buffer control

8-bit timer trigger (Timers 0 and 1)

16-bit timer trigger (Timer 5)

Selecting PG1 shift trigger

7-stage binary counter used

7-stage binary counter not used (Note 1)

Watchdog timer/warm-up timer input control

DB6EN: Double buffer for TREG6

DB4EN: Double buffer for TREG4

TMP93CS41 데이터시트(PDF) 160 Page - Toshiba Semiconductor

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