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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LAN9252/ML 데이터시트(PDF) 273 Page - Microchip Technology |
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LAN9252/ML 데이터시트(HTML) 273 Page - Microchip Technology |
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273 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 273 LAN9252 12.14.60.3 SyncManager x Control Register Note 37: This register can only be written if SyncManager x is disabled via the SyncManager Enable/Disable bit of the SyncManager x Activate Register. Offset: SyncManager x Base Address +4h Size: 8 bits Bits Description ECAT Type PDI Type Default 7 RESERVED Write as 0. RO RO 0b 6 Watchdog Trigger Enable 0: Disabled 1: Enabled R/W Note 37 RO 0b 5 Interrupt in PDI Event Request Register 0: Disabled 1: Enabled R/W Note 37 RO 0b 4 Interrupt in ECAT Event Request Register 0: Disabled 1: Enabled R/W Note 37 RO 0b 3:2 Direction 00: Read: ECAT read access, PDI write access 01: Write: ECAT write access, PDI read access 10: RESERVED 11: RESERVED R/W Note 37 RO 00b 1:0 Operation Mode 00: Buffered (3 buffer mode) 01: RESERVED 10: Mailbox (single buffer mode) 11: RESERVED R/W Note 37 RO 00b |
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