SII3531A datasheet(34/81 Pages) SILICONIMAGE

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PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

SiI-DS-0208-C

5.4 Operation

5.4.1

Command Issuance

Before a command can be executed, it must reside in a slot in SiI3531A RAM and the SiI3531A must be informed that the

PRB is ready to be executed. To accomplish this, the host must issue the command in one of two ways:

Indirect Command Issuance

The indirect method is the most common and flexible method of issuing commands. With this method, the host builds

the PRB in host memory and writes the physical address of the PRB into one of 31 command activation registers,

each associated with a command slot. This causes the SiI3531A to fetch the PRB from host memory and deposit it in

the selected slot of SiI3531A RAM. After the command is fetched, the SiI3531A automatically informs the execution

unit that the command is ready for execution.

The host may issue commands through additional command activation registers at any time without regard as to

whether the previous PRB has been fetched. The SiI3531A will fetch the PRB’s in the order requested when the

necessary resources are available.

Direct Command Issuance

The host may write the 64-byte PRB directly into SiI3531A slot RAM. The RAM area is defined in the port register

map and the host can easily calculate the slot offset to write the PRB. After the PRB is written to RAM, the host

informs the execution unit that it is ready to process by writing the slot number into the command execution FIFO

Please note that when the direct command issue method is used, it is not possible to append scatter/gather entries to

the PRB without defining a LNK in one of the PRB resident scatter/gather entries.

5.4.2

Reset and Initialization

The SiI3531A has a hierarchical reset structure that allows initialization of the entire chip, single port, an attached device, or

the internal command queue. In general, asserting a reset at a high level will cause all underlying circuits to be reset. There

are five levels of reset and initialization possible. The resets, listed from highest to lowest level, are:

5.4.2.1

PERST# Reset

The PERST# reset pin, when asserted, holds the entire chip in a reset state. All configuration, global, and port registers are

initialized to their default state. When de-asserted, PCI Express configuration space is programmable, but the global and port

register spaces and the port state machines/command queue remain in a reset state until the Global and Port Resets are de-

asserted through software control.

5.4.2.2

Global Reset

The Global Reset (Global Control Register, bit 31), when asserted, initializes all global registers, except PHY Configuration,

and all port registers to the default state. All Port Resets are set to one (asserted) while Global Reset is asserted. The Global

Reset must be cleared to zero to allow access to the global register space or to release any Port Reset. Software may use the

Global Reset to initialize all ports with a single operation.

5.4.2.3

Port Reset

Each port contains a Port Reset (Port Control Set/Clear, bit 0) that remains set to one after the Global Reset is cleared to zero.

While Port Reset is asserted, all port registers, except Port PHY Configuration, and OOB Bypass (Port Control Set/Clear, bit

25), are initialized to their default state. The port state machines are reset and the command queue is cleared. The Port

Reset must be cleared to zero by writing a one to bit zero of the Port Control Clear Register to release the Port Reset

condition. Software may assert the port reset condition at any time by writing a one to bit zero of the Port Control Set Register.

5.4.2.4

Device Reset

Each port contains a Device Reset (Port Control Set, bit 1) that may be used by software to reset an attached device without

affecting the contents of the port registers. Writing a one to bit 1 of Port Control Set causes the execution state machines and

pending command queue to be initialized. Then, a COMRESET is transmitted to the attached device. The effect of this

sequence is to clear any outstanding commands and reset the attached device. The Device Reset bit is self-clearing. After

the reset sequence has completed, the bit will be cleared to zero.

5.4.2.5

Port Initialize

Each port contains a Port Initialize (Port Control Set, bit 2) that may be used by software to initialize the port data structures

without affecting the contents of the port registers or resetting the device. Writing a one to bit 1 of Port Control Set causes the

execution state machines and pending command queue to be initialized. The effect of this sequence is to clear any

outstanding commands. The Port Initialize bit is self-clearing. After the initialization sequence has completed, the bit will be

cleared to zero.

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