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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SII3531A 데이터시트(PDF) 39 Page - Silicon image |
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SII3531A 데이터시트(HTML) 39 Page - Silicon image |
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39 / 81 page  PCI Express to Serial ATA Controller Data Sheet Silicon Image, Inc. © 2006 Silicon Image, Inc. SiI-DS-0208-C 39 Interrupt Cause Interrupt Status Bit To Clear: To Enable: To Disable: Masked Raw Command Complete 0 16 If Interrupt W1C == 0 Read Slot Status If Interrupt W1C == 1 Write 1 to Port Interrupt Status bit 0 or 16, OR, write one to desired port bit(s) in Global Interrupt Status. Write 1 to Interrupt Enable Set bit 0 Write 1 to Interrupt Enable Clear bit 0 OR Write 1 to control_interrupt_mask in PRB Control field Command Error 1 17 Write 1 to Interrupt Status bit 1 or 17 Write 1 to Interrupt Enable Set bit 1 Write 1 to Interrupt Enable Clear bit 1 Port Ready 2 18 Write 1 to Interrupt Status bit 2 or 18 Write 1 to Interrupt Enable Set bit 2 Write 1 to Interrupt Enable Clear bit 2 Power Management Change 3 19 Write 1 to Interrupt Status bit 3 or 19 Write 1 to Interrupt Enable Set bit 3 Write 1 to Interrupt Enable Clear bit 3 PHY Ready Change 4 20 Write 1 to Interrupt Status bit 4 or 20 Write 1 to Interrupt Enable Set bit 4 Write 1 to Interrupt Enable Clear bit 4 COMWAKE Received 5 21 Write 1 to Interrupt Status bit 5 or 21 Write 1 to Interrupt Enable Set bit 5 Write 1 to Interrupt Enable Clear bit 5 Unrecognized FIS Received 6 22 Write 1 to Interrupt Status bit 6 or 22 Write 1 to Interrupt Enable Set bit 6 Write 1 to Interrupt Enable Clear bit 6 Device Exchanged 7 23 Write 1 to Interrupt Status bit 7 or 23 Write 1 to Interrupt Enable Set bit 7 Write 1 to Interrupt Enable Clear bit 7 8b/10b Decode Error Threshold 8 24 Write 1 to Interrupt Status bit 8 or 24 OR Write any value to 8b/10b Decode Error Counter bits[15:0] Write non-zero value to 8b/10b Decode Error Counter bits[31:16] Write zero to 8b/10b Decode Error Counter bits[31:16] CRC Error Threshold 9 25 Write 1 to Interrupt Status bit 9 or 25 OR Write any value to CRC Error Counter bits[15:0] Write non-zero value to CRC Error Counter bits[31:16] Write zero to CRC Error Counter bits[31:16] Handshake Error Threshold 10 26 Write 1 to Interrupt Status bit 10 or 26 OR Write any value to Handshake Error Counter bits[15:0] Write non-zero value to Handshake Error Counter bits[31:16] Write zero to Handshake Error Counter bits[31:16] Set Device Bits Notification Received 11 27 Write 1 to Interrupt Status bit 11 or 27 Write 1 to Interrupt Enable Set bit 11 Write 1 to Interrupt Enable Clear bit 11 Table 5-12 Port Interrupt Causes And Control 5.4.8 Command Completion – The Slot Status Register The Slot Status register is designed such that an interrupt service routine can determine the successful completion state of outstanding commands, dismiss the command completion interrupt, and determine if any other enabled interrupt events are pending in a port with a single read of the Slot Status register. The Slot Status Register (Port offset 0x1800 or Global offset 0x00 + (port * 4)) bits 0 through 30 reflect the status of each of the 31 command slots in a port. When a PRB is issued to a command slot, the corresponding bit in the Slot Status register is set to one, indicating that the command is in progress. When a command is successfully completed, the corresponding command slot bit is cleared in the Slot Status register. The host driver may read the Slot Status register at any time to determine the activity state of any issued commands. |
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