PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

© 2006 Silicon Image, Inc.

SiI-DS-0208-C

6

Table of Tables

Table 2-1 Absolute Maximum Ratings.........................................................................................................................................9

Table 2-2 DC Specifications .........................................................................................................................................................9

Table 2-3 SATA Interface DC Specifications..............................................................................................................................10

Table 2-4 PCI Express Interface DC Specifications ...................................................................................................................10

Table 2-5 SATA Interface Timing Specifications ........................................................................................................................11

Table 2-6 SATA Interface Transmitter Output Jitter Characteristics, 1.5 Gb/s ...........................................................................11

Table 2-7 SATA Interface Transmitter Output Jitter Characteristics, 3 Gb/s ..............................................................................11

Table 2-8 PCI Express Interface Timing Specifications..............................................................................................................12

Table 2-9 PCI Express Interface Transmitter Output Jitter Characteristics ................................................................................12

Table 2-10 XTALI Requirements ................................................................................................................................................12

Table 2-11 Power Supply Noise Requirements..........................................................................................................................13

Table 3-1 SiI3531A Pin Listing ...................................................................................................................................................14

Table 3-2 Pin Types ...................................................................................................................................................................14

Table 4-1 Package Dimensions .................................................................................................................................................18

Table 5-1 Scatter/Gather Entry (SGE)........................................................................................................................................23

Table 5-2 Scatter/Gather Table (SGT) .......................................................................................................................................24

Table 5-3 Control Field Bit Definitions ........................................................................................................................................26

Table 5-4 Protocol Override Bit Definitions ................................................................................................................................27

Table 5-5 Port Request Block For Standard ATA Commands ...................................................................................................28

Table 5-6 PRB FIS Area Definition.............................................................................................................................................29

Table 5-7 Port Request Block For PACKET Command .............................................................................................................30

Table 5-8 Port Request Block For Soft Reset Command ...........................................................................................................31

Table 5-9 Port Request Block For External Commands.............................................................................................................32

Table 5-10 Port Request Block For Receiving Interlocked FIS ..................................................................................................33

Table 5-11 Interrupt Steering .....................................................................................................................................................36

Table 5-12 Port Interrupt Causes And Control ...........................................................................................................................39

Table 6-1 SiI3531A PCI Configuration Space ............................................................................................................................43

Table 6-2 SiI3531A Internal Register Space – Base Address 0 .................................................................................................56

Table 6-3 SiI3531A Internal Register Space – Base Address 1 .................................................................................................61

Table 6-4 Port LRAM layout .......................................................................................................................................................62

Table 6-5 Port LRAM Slot layout ................................................................................................................................................62

Table 6-6 Command Activation Register Address Translation ...................................................................................................62

Table 6-7 SActive Indirect Address Translation .........................................................................................................................62

Table 6-8 Command Error Codes ..............................................................................................................................................68

Table 6-9 Default FIS Configurations .........................................................................................................................................69

Table 6-10 SError Register Bits (DIAG Field).............................................................................................................................76

Table 6-11 SiI3531A Internal Register Space – Base Address 2 ...............................................................................................77

Table 7-1 Power Management Register Bits..............................................................................................................................79