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SII3531A 데이터시트(PDF) 69 Page - Silicon image

부품명 SII3531A
상세설명  PCI Express to Serial ATA Controller
PDF  81 Pages
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제조업체  SILICONIMAGE [Silicon image]
홈페이지  http://www.siliconimage.com
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SII3531A 데이터시트(HTML) 69 Page - Silicon image

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PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
© 2006 Silicon Image, Inc.
SiI-DS-0208-C
69
6.3.11 Port FIS Configuration
Address Offset: 1028H
Access Type: Read/Write
Reset Value: 0x1000_1555
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
This register contains bits for controlling Serial ATA FIS reception. For each possible FIS type, a 2-bit code defines the
desired reception behavior as follows:
•
00 – Accept FIS without interlock.
•
01 – Reject FIS without interlock
•
10 – Interlock FIS. Receive FIS into slot reserved for interlocked FIS reception. If no slot has been reserved,
reject the FIS.
•
11 – Reserved.
Bit[1:0] (FISOcfg) defines the 2-bit code for all other FIS types not defined by bits [29:2].
The following table defines the default behavior of FIS configuration.
Table 6-9 Default FIS Configurations
Configuration Bits
FIS
Code
FIS Name
Signals
Default
Value
Default Action
27h
Register (Host to Device)
fis27cfg[1:0]
01b
reject FIS without interlock
34h
Register (Device to Host)
fis34cfg[1:0]
00b
accept FIS without interlock
39h
DMA Activate
fis39cfg[1:0]
00b
accept FIS without interlock
41h
DMA Setup
fis41cfg[1:0]
00b
accept FIS without interlock
46h
Data
fis46cfg[1:0]
00b
accept FIS without interlock
58h
BIST Activate
fis58cfg[1:0]
00b
accept far-end retimed loopback, reject any other
5Fh
PIO Setup
fis5Fcfg[1:0]
00b
accept FIS without interlock
A1h
Set Device Bits
fisa1cfg[1:0]
00b
accept FIS without interlock
A6h
reserved
fisa6cfg[1:0]
01b
reject FIS without interlock
B8h
reserved
fisb8cfg[1:0]
01b
reject FIS without interlock
BFh
reserved
fisbFcfg[1:0]
01b
reject FIS without interlock
C7h
reserved
fisc7cfg[1:0]
01b
reject FIS without interlock
D4h
reserved
fisd4cfg[1:0]
01b
reject FIS without interlock
D9h
reserved
fisd9cfg[1:0]
01b
reject FIS without interlock
Others
reserved
fisocfg[1:0]
01b
reject FIS without interlock



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