SII3531A datasheet(59/81 Pages) SILICONIMAGE

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PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

SiI-DS-0208-C

6.2.6

BIST Pattern Register

Address Offset: 54H

Access Type: Read/Write

Reset Value: 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

BIST Pattern

This register contains the 32-bit fixed pattern that is repeatedly transmitted in data loopback when the BISTpatsel bit (bit 30) of

the BIST Control register is set to 1.

6.2.7

BIST Status Register

Address Offset: 58H

Access Type: Read

Reset Value: 0x8000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Reserved

BISTerrcnt

•

Bit [31]: BISTgood (R) – This bit indicates that all comparisons have been good since initiating data loopback

BIST. This bit is initialized (to 1) when the BISTenable bit is zero in the BIST Control register.

•

Bit [30:12]: Reserved (R). This bit field is reserved and returns zeros on a read.

•

Bit [11:00]: BISTerrcnt (R). This bit field indicates the number of comparisons that have been in error since

initiation of data loopback BIST. This counter is a saturating counter (it stops counting at 0FFFH). This counter

is cleared when the BISTenable bit is zero in the BIST Control register.

6.2.8

MemBIST Status Register

Address Offset: 5CH

Access Type: Read

Reset Value: 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

MemBIST Status

Reserved

•

Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read.

•

Bit [07:00]: MemBIST Status (R). This bit field indicates the status of MemBIST for each RAM. Each status bit

is set to 1 for a successful test.

6.2.9

Configuration Register Offset

Address Offset: 78H

Access Type: Read/Write

Reset Value: 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Reserved

Dword Offset

This register provides indirect addressing of a Configuration Register. The Dword address offset for an indirect access is in

bits 11 to 2; bits 31 to 12, 1, and 0 are reserved and should always be 0.

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