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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STAMP0 데이터시트(PDF) 14 Page - STMicroelectronics |
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STAMP0 데이터시트(HTML) 14 Page - STMicroelectronics |
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14 / 62 page  Architecture STAMP0 14/62 DocID028639 Rev 1 Figure 3: PDM interface sampling control and usage example The PDM_SMP_CLK is generated, together with the microphone clock (PDM_MIC_CLK), inside the Clock Manager block (see Section 5.8: "Clock manager" for more details) and, they have the same frequency (64xFs). However the phase of the PDM_SMP_CLK is selectable employing the I²C register (Reg. 0x08bits: B7, B6, B5), and the supported phase shift values are given in Table 6: "PDM_SMP_CLK phase shift values". PDM-SMP_CLK = PDM_MIC_CLK + phase shift Table 6: PDM_SMP_CLK phase shift values Symbol Parameter Phase shift 000 : 0 degrees 001 : 45 degrees 010 : 90 degrees 011 : 135 degrees 100 : 180 degrees 101 : 225 degrees 110 : 270 degrees 111 : 315 degrees Obsolete Product(s) - Obsolete Product(s) |
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