STAMP0 datasheet(22/62 Pages) STMICROELECTRONICS

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Architecture

STAMP0

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DocID028639 Rev 1

4.5

Serial output interface

The internal architecture of the serial output Interface is depicted in Figure 12: "Serial

output interface architecture", and it consists of a channel mapping and a time division

multiplexing serial interface. In the following subsections the blocks mentioned before will

be detailed.

Figure 12: Serial output interface architecture

4.5.1

Channel mapping

After the downsampling block, the block depicted in Figure 13: "Channel mapping scheme"

allows mapping any of the 8 processed channels to any of the output interface slots. Each

slot consists of the audio data word followed by certain number of empty bits. For example,

a 32-bit slot may consist of a 16-bit audio data word plus 16 empty bits. The SCK clock rate

coming either from the AUTOPLL block (SCK_RATE signal when the PLL is automatically

programmed) or directly from the I²C register (Reg. 0x09 bit B4 and B3 when the PLL is

programmed manually), and the slot size, coming from the I²C register (Reg. 0x09 bit B5),

together define the number of slots available in a frame. In fact, as depicted in Figure 13:

"Channel mapping scheme", five possible frames are supported: 64Fs16, 64Fs32,

128Fs16, 128Fs32 and 256Fs32.

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