STAMP0 datasheet(25/62 Pages) STMICROELECTRONICS

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STAMP0

Architecture

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Figure 17: Data and FSY change on the rising edges of SCK and are valid on the falling edges

of SCK.The frame starts on the falling edge of FSY (NO DELAY)

Within one frame, the DATA is divided into multiple slots as defined in Section 5.5.1:

"Channel mapping".

The TDM interface supports the non-delayed (Figure 14: "Data and FSY change on the

falling edges of SCK and are valid on the rising edges of SCK. The frame starts on the

rising edge of FSY (NO DELAY)", Figure 15: "Data and FSY change on the rising edges of

SCK and are valid on the falling edges of SCK. The frame starts on the rising edge of FSY

(NO DELAY)", Figure 16: "Data and FSY change on the falling edges of SCK and are valid

on the rising edges of SCK.The frame starts on the falling edge of FSY (NO DELAY)" and

Figure 17: "Data and FSY change on the rising edges of SCK and are valid on the falling

edges of SCK.The frame starts on the falling edge of FSY (NO DELAY)") sequential

alignment and delayed sequential alignment data formats.

In the latter, as shown in Figure 18: "Data and FSY change on the falling edges of SCK

and are valid on the rising edges of SCK.The frame starts on the rising edge of FSY

(DELAYED)", there is one SCK clock delay between the start/stop of the frame and the

start/stop of the TDM data.

Figure 18: Data and FSY change on the falling edges of SCK and are valid on the rising edges

of SCK.The frame starts on the rising edge of FSY (DELAYED)

The non-delayed and delayed alignments can be selected through the I²C register (Reg.

0x09 bit B6). The sequential (non-delayed) alignment is the default format.

4.6

I²C interface

In the STAMP0 each module contains several registers for configuration, status and

testing, each one can be accessed using an I²C standard serial interface. A detailed

description of the protocol is given in the following subsections.

4.6.1

I²C communication protocol

The STAMP0 supports the I²C protocol via the input ports SCL and SDA (master to slave

communication). This protocol defines any device that sends data to the bus as a

transmitter and any device that reads the data as a receiver. The device that controls the

data transfer is known as the master and the other as the slave. The master always starts

the transfer and provides the serial clock for synchronization.

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