STAMP0 datasheet(28/62 Pages) STMICROELECTRONICS

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Architecture

STAMP0

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DocID028639 Rev 1

4.8

Clock manager

The clock manager handles all the internal and external clocks of the device. The internal

architecture of the clock manager is depicted in Figure 21: "Clock manager architecture". In

the subsections below a detailed description of the clock manager internal blocks is given.

Figure 21: Clock manager architecture

4.8.1

PLL

The PLL employed in the STAMP0 device belongs to the class of charge pump PLLs. Its

internal architecture is depicted in Figure 22: "PLL block internal architecture", and the

internal key blocks are detailed below.

The input frequency divider divides the PLL Input frequency by a factor called the Input

Division Factor (IDF). The divided frequency (INFIN) is the input to the Phase/Frequency

Detector (PFD) of PLL.

The PFD block compares the phase difference between the corresponding rising edges of

INFIN and clock output from the Loop Frequency Divider (FBCLK), and it generates voltage

pulses with width proportional to the phase difference. The charge pump and loop filter

block convert the voltage pulses from the PFD to current pulses which charge the PLL

Loop Filter to generate the control voltage for the Voltage Controlled Oscillator (VCO).

Obsolete

Product(s)

- Obsolete

Product(s)

STAMP0 데이터시트(PDF) 28 Page - STMicroelectronics