STAMP0 datasheet(24/62 Pages) STMICROELECTRONICS

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Architecture

STAMP0

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vice versa (Figure 15: "Data and FSY change on the rising edges of SCK and are valid on

the falling edges of SCK. The frame starts on the rising edge of FSY (NO DELAY)" and

Figure 17: "Data and FSY change on the rising edges of SCK and are valid on the falling

edges of SCK.The frame starts on the falling edge of FSY (NO DELAY)"). This can be

configured through the I²C register (Reg. 0x09 bit B2).

However, by default the TDM data and FSY signals change on the falling edges of the SCK

and are valid on the rising edges.

The FSY signal is used to identify the beginning and the end of a frame. Two possible

solutions are supported: the frame data start/stop on the rising edge of FSY ( Figure 14:

"Data and FSY change on the falling edges of SCK and are valid on the rising edges of

SCK. The frame starts on the rising edge of FSY (NO DELAY)" and Figure 15: "Data and

FSY change on the rising edges of SCK and are valid on the falling edges of SCK. The

frame starts on the rising edge of FSY (NO DELAY)"); frame data start/stop on the falling

edge of SCK (Figure 16: "Data and FSY change on the falling edges of SCK and are valid

on the rising edges of SCK.The frame starts on the falling edge of FSY (NO DELAY)" and

Figure 17: "Data and FSY change on the rising edges of SCK and are valid on the falling

edges of SCK.The frame starts on the falling edge of FSY (NO DELAY)"). This can be

configured through the I²C register (Reg. 0x09 bit B1), and by default the frame starts on

the rising edge of FSY.

While the frame rate is usually the same as the audio sample rate such as 44.1 kHz and 48

kHz, the serial clock rate is a multiple of the frame rate. For example, SCK rate can be

configured to be 64xFs, 128xFs and 256xFs through the I²C.

The width of the FSY signal pulse can vary from one serial clock to the highest supported

SCK clock rate minus one. For example, on a system that supports 256xFs, the pulse width

of the FSY signal can be from one SCK to 255 SCK clocks. So, the duty cycle of the FSY

signal can vary and does not have to be 50%.

Figure 14: Data and FSY change on the falling edges of SCK and are valid on the rising edges

of SCK. The frame starts on the rising edge of FSY (NO DELAY)

Figure 15: Data and FSY change on the rising edges of SCK and are valid on the falling edges

of SCK. The frame starts on the rising edge of FSY (NO DELAY)

Figure 16: Data and FSY change on the falling edges of SCK and are valid on the rising edges

of SCK.The frame starts on the falling edge of FSY (NO DELAY)

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