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L99PM72PXP 데이터시트(PDF) 70 Page - STMicroelectronics

부품명 L99PM72PXP
상세설명  Advanced power management system IC with embedded LIN and high speed CAN transceiver supporting CAN Partial Networking
PDF  128 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99PM72PXP 데이터시트(HTML) 70 Page - STMicroelectronics

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Electrical specifications
L99PM72PXP
70/128
Doc ID 023553 Rev 3
5.5.14
SPI
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6V<VS <18V; 4.5V<V1 < 5.3 V; all outputs open; Tj = -40°C to 130°C, unless otherwise
specified.
Table 36.
Input: CSN
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VCSNLOW
Input voltage low level
Normal mode, V1 = 5 V
1.35
1.8
V
VCSNHIGH
Input voltage high level
Normal mode, V1 =5V
2
2.9
V
VCSNHYS
VCSNHIGH - VCSNLOW
Normal mode, V1 = 5 V
0.6
1.0
1.5
V
ICSNPU
CSN pull up resistor
Normal mode, V1 =5V
10
20
35
k
Table 37.
Inputs: CLK, DI
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tset
Delay time from
standby to active
mode
Switching from standby to active
mode. Time until output drivers
are enabled after CSN going to
high.
160
300
µs
VIN L
Input low level
V1 = 5 V
1.35
2.05
2.75
V
VIN H
Input high level
V1 = 5 V
1.9
2.8
3.7
V
VIN Hyst
Input hysteresis
V1 = 5 V
0.4
0.75
1.5
V
I in
Pull down current
at input
VIN = 1.5 V
5
30
60
µA
Cin
(1)
1.
Value of input capacity is not measured in production test. Parameter guaranteed by design.
Input capacitance
at input CSN, CLK,
DI and PWM1,2
0V<V1 <5.3 V
10
15
pF
fCLK
SPI input
frequency at CLK
1MHz
Table 38.
DI timing(1)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tCLK
clock period
V1 = 5 V
1000
—
ns
tCLKH
clock high time
V1 = 5 V
400
—
ns
tCLKL
clock low time
V1 = 5 V
400
—
ns
tset CSN
CSN setup time, CSN low before
rising edge of CLK
V1 = 5 V
400
—
ns
tset CLK
CLK setup time, CLK high
before rising edge of CSN
V1 = 5 V
400
—
ns
tset DI
DI setup time
V1 = 5 V
200
—
ns



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