L99PM72PXP datasheet(76/128 Pages) STMICROELECTRONICS

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ST SPI

L99PM72PXP

76/128

Doc ID 023553 Rev 3

ST SPI

6.1

SPI communication flow

6.1.1

General description

The SPI communication is based on a standard SPI interface structure using CSN (Chip

Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock) signal

lines.

At device start-up the master reads the <SPI-frame-ID> register (ROM address 3EH) of the

slave device. This 8-bit register indicates the SPI frame length (24bit) and the availability of

additional features.

Each communication frame consists of an instruction byte which is followed by two data

bytes.

The data returned on SDO within the same frame always starts with the <Global Status>

bytes (i. e. ‘In-frame-response’).

For Write cycles the <Global Status> register is followed by the previous content of the

addressed register.

For Read cycles the <Global Status> register is followed by the content of the addressed

A Write command is only accepted as a valid command by the device if the counted number

of clocks is exact 24, otherwise the command is rejected.

Command Byte

Each communication frame starts with a command byte. It consists of an operating code

which specifies the type of operation (<Write>, <Read>, <Read and Clear>, <Read Device

Information>) and a 6 bit address. If less than 6 address bits are required, the remaining bits

are unused but are reserved.

OCx: Operating Code

Ax: Address

Table 44.

Command Byte

MSB

LSB

Op Code

Address

OC1

OC0

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