XIO2001IPNP datasheet(110/145 Pages) TI2

110 / 145 page

Table 8-81. Serial IRQ Status Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

1(1)

IRQ1

RCU

IRQ 1 asserted. This bit indicates that the IRQ1 has been asserted.

0 = Deasserted

1 = Asserted

0(1)

IRQ0

RCU

IRQ 0 asserted. This bit indicates that the IRQ0 has been asserted.

0 = Deasserted

1 = Asserted

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.6.12 Pre-Fetch Agent Request Limits Register

This register is used to set the Pre-Fetch Agent's limits on retrieving data using upstream reads. This register is

an alias for the pre-fetch agent request limits register in the classic PCI configuration space (offset E8h, see

Section 8.4.76). See Table 8-82 for a complete description of the register contents.

Device control memory window register offset:

50h

Read/Clear

Default value:

0443h

BIT NUMBER

RESET STATE

Table 8-82. Pre-Fetch Agent Request Limits Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:12

RSVD

Reserved. Returns 0h when read.

11:8(1)

PFA_REQ_

CNT_LIMIT

Request count limit. Determines the number of Pre-Fetch reads that takes place in each

burst.

4'h0 = Auto-prefetch agent is disabled.

4'h1 = Thread is limited to one buffer. No auto-prefetch reads will be generated.

4'h2:F = Thread will be limited to initial read and (PFA_REQ_CNT_LIMIT – 1)

7:6

PFA_CPL_CACHE_

MODE

Completion cache mode. Determines the rules for completing the caching process.

00 = No caching.

•

Pre-fetching is disabled.

•

All remaining read completion data will be discarded after any of the data has been

returned to the PCI master.

01 = Light caching.

•

Pre-fetching is enabled.

•

All remaining read completion data will be discarded after data has been returned to

the PCI master and the PCI master terminated the transfer.

•

All remaining read completion data will be cached after data has been returned to the

PCI master and the bridge has terminated the transfer with RETRY.

10 = Full caching.

•

Pre-fetching is enabled.

•

All remaining read completion data will be cached after data has been returned to the

PCI master and the PCI master terminated the transfer.

•

All remaining read completion data will be cached after data has been returned to the

PCI master and the bridge has terminated the transfer with RETRY.

11 = Reserved.

5:4

RSVD

Reserved. Returns 00b when read.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

www.ti.com

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