XIO2001IPNP datasheet(107/145 Pages) TI2

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8.6.9 Serial IRQ Mode Control Register

This register controls the behavior of the serial IRQ controller. This register is an alias for the serial IRQ mode

control register in the classic PCI configuration space (offset E0h, see Section 8.4.73). See Table 8-56 for a

complete description of the register contents.

Device control memory window register offset:

48h

Read-only, Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 8-79. Serial IRQ Mode Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

RSVD

Reserved. Returns 0h when read.

3:2(1)

START_WIDTH

Start frame pulse width. Sets the width of the start frame for a SERIRQ stream.

00 = 4 clocks (default)

01 = 6 clocks

10 = 8 clocks

11 = Reserved

1(1)

POLLMODE

Poll mode. This bit selects between continuous and quiet mode.

0 = Continuous mode (default)

1 = Quiet mode

0(1)

DRIVEMODE

RW Drive mode. This bit selects the behavior of the serial IRQ controller during the

recovery cycle.

0 = Drive high (default)

1 = 3-state

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.6.10 Serial IRQ Edge Control Register

This register controls the edge mode or level mode for each IRQ in the serial IRQ stream. This register is an

alias for the serial IRQ edge control register in the classic PCI configuration space (offset E2h, see Section

8.4.74). See Table 8-80 for a complete description of the register contents.

Device control memory window register offset:

4Ah

Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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