TMS320VC5502 datasheet(67/190 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

3.10.5.9 CLKOUT3 Select Register (CK3SEL)

This register controls which clock is output onto the CLKOUT3 so that it may be used to test and debug

the PLL (in addition to its normal function of being a direct input clock divider). Modes other than

CK3SEL = 1011 are intended for debug use only and should not be used during normal operation.

Reserved

R, 00000000

Reserved

CK3SEL

R, 0000

R/W, 1011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-23. CLKOUT3 Select Register Layout (0x1C82)

Table 3-21. CLKOUT3 Select Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15:4

000000000000

Reserved. Reads return 0. Writes have no effect.

CK3SEL

3:0

R/W

1011

Output on CLK3SEL pin(1)

•

CK3SEL = 1001: CLKOUT3 becomes point A in Figure 3-14

•

CK3SEL = 1010: CLKOUT3 becomes point B in Figure 3-14

•

CK3SEL = 0000-0111: CLKOUT3 becomes oscillator divider output

in Figure 3-14

•

CK3SEL = 1011: CLKOUT3 becomes point C in Figure 3-14

•

CK3SEL = Other: Not supported

(1)

The different options for the CLKOUT3 signal are intended for test purposes; it is recommended that the CK3SEL bits of the CK3SEL

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