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TMS320VC5502 데이터시트(PDF) 83 Page - Texas Instruments |
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TMS320VC5502 데이터시트(HTML) 83 Page - Texas Instruments |
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83 / 190 page ![]() www.ti.com TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166J – APRIL 2001 – REVISED AUGUST 2006 Table 3-31. Peripheral IDLE Status Register Bit Field Description (continued) BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION SP0 2 R 0 McBSP0 bit • SP0 = 0: McBSP0 is active • SP0 = 1: McBSP0 is disabled TIM1 1 R 0 TIMER1 bit • TIM1 = 0: TIMER1 is active • TIM1 = 1: TIMER1 is disabled TIM0 0 R 0 TIMER0 bit • TIM0 = 0: TIMER0 is active • TIM0 = 1: TIMER0 is disabled 3.11.7.5 Master IDLE Control Register (MICR) 15 8 Reserved R, 00000000 7 2 1 0 Reserved HPI DMA R, 000000 R/W, 0 R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-30. Master IDLE Control Register Layout (0x9402) Table 3-32. Master IDLE Control Register Bit Field Description BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION Reserved 15-2 R 00000000000000 Reserved HPI 1 R/W 0 HPI bit • HPI = 0: HPI remains active when ISTR.MPIS becomes 1 • HPI = 1: HPI is disabled when ISTR.MPIS becomes 1 DMA 0 R/W 0 DMA bit • DMA = 0: DMA remains active when ISTR.MPIS becomes 1 • DMA = 1: DMA is disabled when ISTR.MPIS becomes 1 Submit Documentation Feedback Functional Overview 83 |
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