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TMS320VC5502 데이터시트(PDF) 85 Page - Texas Instruments |
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TMS320VC5502 데이터시트(HTML) 85 Page - Texas Instruments |
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85 / 190 page ![]() www.ti.com TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166J – APRIL 2001 – REVISED AUGUST 2006 3.12.1.1 General-Purpose I/O Direction Register (IODIR) 15 8 Reserved R, 00000000 7 6 5 4 3 2 1 0 IO7DIR IO6DIR IO5DIR IO4DIR IO3DIR IO2DIR IO1DIR IO0DIR R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-32. GPIO Direction Register Layout (0x3400) Table 3-34. GPIO Direction Register Bit Field Description (1) BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION Reserved 15-8 R 00000000 Reserved IOxDIR 7-0 R/W 00000000 Data direction bits that configure the GPIO pins as inputs or outputs. • IOxDIR = 0: Configure corresponding GPIO pin as an input • IOxDIR = 1: Configure corresponding GPIO pin as an output (1) x = value from 0 to 7 3.12.1.2 General-Purpose I/O Data Register (IODATA) 15 8 Reserved R, 00000000 7 6 5 4 3 2 1 0 IO7D IO6D IO5D IO4D IO3D IO2D IO1D IO0D R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin. Figure 3-33. GPIO Data Register Layout (0x3401) Table 3-35. GPIO Data Register Bit Field Description (1) BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION Reserved 15-8 R 00000000 Reserved IOxD 7-0 R/W Depends on the signal level on Data bits that are used to control the level of the I/O the corresponding I/O pin pins configured as outputs and to monitor the level of the I/O pins configured as inputs. If IOxDIR = 0, then: • IOxD = 0: Corresponding GPIO pin is read as a low • IOxD = 1: Corresponding GPIO pin is read as a high If IOxDIR = 1, then: • IOxD = 0: Set corresponding GPIO pin to low • IOxD = 1: Set corresponding GPIO pin to high (1) x = value from 0 to 7 Submit Documentation Feedback Functional Overview 85 |
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