TMS320VC5502 datasheet(84/190 Pages) TI

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3.12 General-Purpose I/O (GPIO)

3.12.1

General-Purpose I/O Port

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

3.11.7.6 Master IDLE Status Register (MISR)

Reserved

R, 00000000

Reserved

HPI

DMA

R, 000000

R, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-31. Master IDLE Status Register Layout (0x9403)

Table 3-33. Master IDLE Status Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15-2

00000000000000

Reserved

HPI

HPI bit

•

HPI = 0: HPI is active

•

HPI = 1: HPI is in IDLE status

DMA

DMA bit

•

DMA = 0: DMA is active

•

DMA = 1: DMA is in IDLE status

The 5502 includes an 8-bit I/O port solely for general-purpose input and output. Several dual-purpose

(multiplexed) pins complement the dedicated GPIO pins. The following sections describe the 8-bit GPIO

port as well as the dual GPIO functions of the Parallel Port Mux and Host Port Mux pins.

The general-purpose I/O port consists of eight individually bit-selectable I/O pins GPIO0 (LSB) through

GPIO7 (MSB). The I/O port is controlled using two registers—IODIR and IODATA—that can be accessed

by the CPU or by the DMA, via the peripheral bus controller. The General-Purpose I/O Direction Register

(IODIR) is mapped at address 0x3400, and the General-Purpose I/O Data Register (IODATA) is mapped

at address 0x3401.

The GPIO3 and GPIO5 pins are multiplexed with the CLKX2 and FSX2 signals through the SP0 and SP2

pins, respectively. The function of the SP0 and SP2 pins is determined by the state of the GPIO7 pin

during reset. The SP0 and SP2 pins are set to GPIO3 and GPIO5, respectively, if GPIO7 is low during

reset. The SP0 and SP2 pins are set to CLKX2 and FSX2, respectively, if GPIO7 is high during reset. The

function of the SP0 and SP2 pins will be set once the device is taken out of reset (RESET pin transitions

from a low to a high state).

Figure 3-32 and Figure 3-33 show the bit layout of IODIR and IODATA, respectively. Table 3-34 and

Table 3-35 describe the bit fields of these registers.

Functional Overview

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