CMV2000 datasheet(31/87 Pages) AMSOSRAM

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CMV2000

Functional description

Datasheet

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The CLK_IN master clock (48 MHz for 480 Mbps in 10-bit mode) should only start after the rise

time of the supplies. The

external reset pin should be released at least 1 μs after the supplies

have become stable. The first frame can be requested 1 μs after the reset pin has been

released.

If the register settings need to be changed (e.g. when using 12-bit mode), this can be done

through an SPI upload 1 µs after the rising edge on the SYS_RES_N pin, as described in

Figure 18. In this case, the FRAME_REQ pulse must not be sent until after the SPI upload is

completed, plus a settling time. This settling time is to ensure that the changes programmed in

the SPI upload have taken effect before an image is captured. The main factor that determines

this settling time is the change in ADC gain, because the voltage over the ramp capacitor has

to settle. For typical applications, where the ADC gain is changed from the default value of 32

to a value that saturates the ADC output (40 to 45 at 48 MHz), the settling time is 5 ms. In

extreme cases, when the gain is changed from default to the maximum value, the settling time

will increase to 20 ms.

Figure 18: Start-up sequence for 12-bit mode

7.2.7

Reset sequence

If a sensor reset is necessary while the sensor is running, the sequence in Figure 19 should be

followed. The on-board sequencer will be reset and all programming registers will return to

their default start-up values when a falling edge is detected on the SYS_RES_N pin. As with

the start-

up sequence, there is a minimum time of 1 μs plus a settling time needed before a

FRAME_REQ pulse can be sent, to allow the gain settings to settle at their default value.

1μs

Stable time

Supply

CLK_IN

SYS_RES_N

FRAME_REQ

SPI upload

1μs

Settling time

CMV2000 데이터시트(PDF) 31 Page - ams-OSRAM AG