CMV2000 datasheet(64/87 Pages) AMSOSRAM

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CMV2000

Functional description

Datasheet

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DS000734

• v8-00 • 2025-Jul-07

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7.5.4

Data rate

Information:

This is only applicable for Version 2.

During start-up or after a sequencer reset, the data rate can be changed if a lower speed than

480 Mbps is desired. This can be done by applying a lower master input clock (CLK_IN) and

high speed LVDS clock (LVDS_CLK_N/P) to the sensor. See chapter 7.2.4 for more details on

the input clock and chapter 7.2.5 for details on how the data rate can be changed. No registers

have to be changed when using a data rate different from 480 Mbps.

7.5.5

Power control

The power consumption of the CMV2000 can be decreased by disabling the LVDS data

channels when they are not used (in 8, 4 or 2 outputs mode). The power will decrease with

approximately 18 mW per channel. So, reducing the outputs from 16 to 4 will save you about

216 mW or 33%. This is the main source for saving power. Other settings (such as bitrate, fps,

temperature …) will have very little to no effect on the total power consumption.

Table 27: Power control register settings

Default value

Description of the value

Channel_en

80[7:0]

81[7:0]

82[2:0]

All ‘1’

Bits 0-15 enable/disable the data output channels

Bit 16 enables/disables the clock channel

Bit 17 enables/disables the control channel

Bit 18 enables/disables the LVDS clock input

0: Disabled

1: Enabled

Decreasing the master clock frequency and thereby the LVDS clock frequency will also

decrease power consumption albeit little. Decreasing the LVDS_CLK frequency from 480 MHz

to 128 MHz will decrease power consumption with about 25 mW. All power savings will

happen on the VDD20 supply. Other settings or factors have little to no effect on power

consumption.

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