PSD913F2 datasheet(52/94 Pages) STMICROELECTRONICS

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PSD9XX Family

Preliminary Information

Drive

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Port A

Open

Slew

Drain

Rate

Port B

Open

Slew

Drain

Rate

Port D

Slew

Rate

Table 27. Drive Register Pin Assignment

NOTE: NA = Not Applicable.

The

PSD9XX

Functional

Blocks

(cont.)

9.4.3.3 Drive Select Register

The Drive Select Register configures the pin driver as Open Drain or CMOS for some port

pins, and controls the slew rate for the other port pins. An external pull-up resistor should

be used for pins configured as Open Drain.

A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register

is set to a ‘1’. The default pin drive is CMOS.

Aside: the slew rate is a measurement of the rise and fall times of an output. A higher

slew rate means a faster output response and may create more electrical noise. A pin

operates in a high slew rate when the corresponding bit in the Drive Register is set to ‘1’.

The default rate is slow slew.

Table 27 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can

be configured as Open Drain outputs and which pins the slew rate can be set for.

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