PSD913F2 datasheet(59/94 Pages) STMICROELECTRONICS

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Preliminary Information

PSD9XX Family

The

PSD9XX

Functional

Blocks

(cont.)

Access

5V VCC,

PLD

Memory

Recovery Time

Typical

Propagation

Access

to Normal

Standby

Mode

Delay

Time

Access

Current

Power Down

Normal tpd

No Access

tLVDV

75 µA

(Note 1)

(Note 2)

Table 30. PSD9XX Timing and Standby Current During Power

Down Mode

NOTES: 1. Power Down does not affect the operation of the PLD. The PLD operation in this

mode is based only on the Turbo Bit.

2. Typical current consumption assuming no PLD inputs are changing state and

the PLD Turbo bit is off.

Port Function

Pin Level

MCU I/O

No Change

PLD Out

No Change

Address Out

Undefined

Data Port

Three-State

Table 29. Power Down Mode’s Effect on

Ports

9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.)

Power Down Mode

By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled.

The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive

for fifteen CLKIN (pin PD1) clock periods.

The following should be kept in mind when the PSD is in Power Down Mode:

• If the address strobe starts pulsing again, the PSD will return to normal operation.

The PSD will also return to normal operation if either the CSI input returns low or the

Reset input returns high.

• The MCU address/data bus is blocked from all memories and PLDs.

• Various signals can be blocked (prior to Power Down Mode) from entering the PLDs

by setting the appropriate bits in the PMMR registers. The blocked signals include

MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from

the PLDs will not block CLKIN from the APD unit.

• All PSD memories enter Standby Mode and are drawing standby current. However,

the PLDs and I/O ports do not go into Standby Mode because you don’t want to

have to wait for the logic and I/O to “wake-up” before their outputs can change. See

table 29 for Power Down Mode effects on PSD ports.

• Typical standby current is in µA for 5 V parts. This standby current value assumes

that there are no transitions on any PLD input.

HC11 (or compatible) Users Note

The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11

(or compatible) in your design, and you wish to use the Power Down, you must not

connect the E clock to the CLKIN input (PD1). You should instead connect an

independent clock signal to the CLKIN input. The clock frequency must be less than

15 times the frequency of AS. The reason for this is that if the frequency is greater than

15 times the frequency of AS, the PSD9XX will keep going into Power Down Mode.

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