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PSD913F2 데이터시트(PDF) 60 Page - STMicroelectronics |
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PSD913F2 데이터시트(HTML) 60 Page - STMicroelectronics |
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60 / 94 page ![]() PSD9XX Family Preliminary Information 56 APD EN PMMR0 BIT 1=1 ALE RESET CSI CLKIN TRANSITION DETECTION EDGE DETECT APD COUNTER POWER DOWN (PDN) DISABLE BUS INTERFACE SECONDARY FLASH SELECT MAIN FLASH SELECT SRAM SELECT PD CLR PD DISABLE MAIN FLASH / SECONDARY FLASH /SRAM PLD SELECT Figure 23. APD Logic Block The PSD9XX Functional Blocks (cont.) Enable APD Set PMMR0 Bit 1 = 1 PSD in Power Down Mode ALE/AS idle for 15 CLKIN clocks? RESET Yes No OPTIONAL Disable desired inputs to PLD by setting PMMR0 bit 4 and PMMR2 bits 2 through 6. Figure 24. Enable Power Down Flow Chart |
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