STLS2F01 datasheet(30/48 Pages) STMICROELECTRONICS

30 / 48 page

DDR2 SDRAM controller interface description

STLS2F01

30/48

DLL_DQS_DELAY_BYPASS_0

56:48

0x0

0x0-0x1ff

Number of delay elements to include

in the DQS signal from the DRAMs

for dll_rd_dqs_slice 0 during reads

when DLL is being bypassed.

TRFC

47:40

0x0

0x0-0xff

DRAM TRFC parameter in cycles.

TRCD_INT

39:32

0x0

0x0-0xff

DRAM TRCD parameter in cycles.

CONF_CTL_13[31:0]

Offset: 0xd0

DDR2 667:0x002a002a

DLL_DQS_DELAY_BYPASS_2

24:16

0x0

0x0-0x1

Number of delay elements to include

in the DQS signal from the DRAMs

for dll_rd_dqs_slice 2 during reads

when DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_1

8:0

0x0

0x0-0x1

Number of delay elements to include

in the DQS signal from the DRAMs

for dll_rd_dqs_slice 1 during reads

when DLL is being bypassed.

CONF_CTL_13[63:32]

Offset: 0xd0

DDR2 667:0x002a002a

DLL_DQS_DELAY_BYPASS_4

56:48

0x0

0x0-0x1ff

Number of delay elements to include

in the DQS signal from the DRAMs

for dll_rd_dqs_slice 4 during reads

when DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_3

40:32

0x0

0x0-0x1ff

Number of delay elements to include

in the DQS signal from the DRAMs

for dll_rd_dqs_slice 3 during reads

when DLL is being bypassed.

CONF_CTL_14[31:0]

Offset: 0xe0

DDR2 667:0x002a002a

DLL_DQS_DELAY_BYPASS_6

24:16

0x0

0x0-0x1ff

Number of delay elements to include

in the DQS signal from the DRAMs

for dll_rd_dqs_slice 6 during reads

when DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_5

8:0

0x0

0x0-0x1ff

Number of delay elements to include

in the DQS signal from the DRAMs

for dll_rd_dqs_slice 7 during reads

when DLL is being bypassed.

CONF_CTL_14[63:32]

Offset: 0xe0

DDR2 667:0x002a002a

DLL_DQS_DELAY_BYPASS_8

56:48

0x0

0x0-0x1ff

Number of delay elements to include

in the DQS signal from the DRAMs

for dll_rd_dqs_slice 8 during reads

when DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_7

40:32

0x0

0x0-0x1ff

Number of delay elements to include

in the DQS signal from the DRAMs

for dll_rd_dqs_slice 7 during reads

when DLL is being bypassed.

CONF_CTL_15[31:0]

Offset: 0xf0

DDR2 667:0x00000004

Table 12.

DDR SDRAM configuration parameter register format (continued)

Parameters

Bits

Default

value

Range

Description

STLS2F01 데이터시트(PDF) 30 Page - STMicroelectronics

STLS2F01 데이터시트(HTML) 30 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

데이터시트 다운로드

링크 URL