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STLS2F01 데이터시트(PDF) 33 Page - STMicroelectronics

부품명 STLS2F01
상세설명  Loongson 2F: High performance 64-bit superscalar MIPS® microprocessor
PDF  48 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STLS2F01 데이터시트(HTML) 33 Page - STMicroelectronics

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STLS2F01
DDR2 SDRAM controller interface description
33/48
Note:
1.
CONF_CTL_00 AP
The parameter determines whether the auto pre-charge function is enabled. Once the
function is enabled, memory will close the page, after each write/read instruction. If
mass continuous address operation happens, the parameter will caused the
performance degradation.
2.
CONF_CTL_00 CONCURRENTAP
The parameter determines whether the concurrent auto pre-charge function is enabled.
Most of SDRAM vendors do not support this feature.
3.
CONF_CTL_03 SREFRESH
The parameter is used set the self-refresh style. It must be set 0, when returning from
self-refresh.
4.
CONF_CTL_07 CASLAT_LIN_GATE
The parameter is used to control the data sample of memory controller when read
PORT_CMD_ERROR_ADDR[31
:0]
31:0
0x0
0x0-
0x1ffffffff
Address of port that caused the
PORT command error. Read-only.
CONF_CTL_24[63:32]
Offset: 0x180
DDR2 667:0x00000000
PORT_CMD_ERROR_ADDR[36
:32]
36:32
0x0
0x0-
0x1ffffffff
Address of port that caused the
PORT command error. Read-only
CONF_CTL_25[31:0]
Offset: 0x190
DDR2 667:0x00000000
ECC_C_DATA[31:0]
31:0
0x0
0x0-
0x1ffffffff
Data associated with correctable
ECC event. Read-only.
CONF_CTL_25[63:32]
Offset: 0x190
DDR2 667:0x00000000
ECC_C_DATA[63:32]
63:32
0x0
0x0-
0x1ffffffff
Data associated with correctable
ECC event. Read-only.
CONF_CTL_26[31:0]
Offset: 0x1a0
DDR2 667:0x00000000
ECC_U_DATA[31:0]
31:0
0x0
0x0-
0x1ffffffff
Data associated with uncorrectable
ECC event. Read-only.
CONF_CTL_26[63:32]
Offset: 0x1a0
DDR2 667:0x00000000
ECC_U_DATA[63:32]
63:32
0x0
0x0-
0x1ffffffff
Data associated with uncorrectable
ECC event. Read-only.
CONF_CTL_27[63:32]
Offset: 0x1b0
DDR2 667:0x00000000
CKE_DELAY
2:0
0x0
0x0-0x7
Additional cycles to delay CKE for
status reporting.
CONF_CTL_28[63:32]
Offset: 0x1c0
DDR2 667:0x00000001
UB_DIMM
0:0
0x0
0x0-0x1
Enable unbuffered DIMM.
Table 12.
DDR SDRAM configuration parameter register format (continued)
Parameters
Bits
Default
value
Range
Description



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