STLS2F02 datasheet(6/49 Pages) STMICROELECTRONICS

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Introduction

STLS2F02

6/49

Introduction

STLS processors are based on the Loongson CPU architecture licensed by

STMicroelectronics from the Institute of Computing Technology (ICT), which is part of the

Chinese Academy of Science. The STLS family contains 64-bit high-end processors for

applications requiring high levels of performance and efficiency in terms of cost, power

consumption and area.

The Loongson CPU architecture is compatible in user mode at the MIPSIII level of the

MIPS64-bit architecture.

This microprocessor achieves a leading position in the MIPS family for its combination of

multiple features, including high clock frequency, out-of-order superscalar execution and

ability to run single-instruction-multiple data (SIMD).

STLS processors implement a superscalar, out-of-order execution pipeline with dynamic

branch prediction and non-blocking cache.

Figure 1.

Block diagram

L2 cache

DDR2

333MHz DDR

Controller

Cache Interface

Writeback

Queue

Miss

Queue

Refill Bus

Branch Bus

BTB

BHT

BRQ

Fix

Float

Integer

File

Floating

Point

File

Map Bus

ROQ

ALU1

ALU2

AGU

FPU1

TLB

CP0

Queue

D-Cache

64KB

FPU2

ITLB

I-Cache

64KB

Commit Bus

Writeback Bus

Reorder Queue

AXI Crossbar

133MHz PCIX

Local IO GPIO, INT

IO Controller

AC00117

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