STLS2F02 datasheet(40/49 Pages) STMICROELECTRONICS

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Electrical characteristics

STLS2F02

40/49

6.4

AC parameters

Table 17.

Clock parameters

(Test conditions:SYSCLK=100 MHz, PCICLK=133 MHz, MEMCLK=333 MHz,

CoreClk=1000 MHz)

Parameter

Min

Typ

Max

Unit

SYSCLK high level time

SYSCLK low level time

SYSCLK rising time

SYSCLK falling time

SYSCLK cycle variation

±300

PCI_CLK high level time

PCI_CLK low level time

PCI_CLK rising slew

1.5

V/ns

PCI_CLK falling slew

1.5

V/ns

PCI_CLK cycle variation

±500

MEMCLK high level time

1.41

1.59

MEMCLK low level time

1.41

1.59

MEMCLK rising slew

V/ns

MEMCLK falling slew

V/ns

MEMCLK cycle variation

±225

DQS high level time

1.35

1.65

DQS low level time

1.35

1.65

DQS rising slew

V/ns

DQS falling slew

V/ns

DQS cycle variation

±225

Table 18.

Input setup and hold time

(Test conditions:SYSCLK=100 MHz, PCICLK=133 MHz, MEMCLK=333 MHz,

CoreClk=1000 MHz)

Parameter

Min

Typ

Max

Unit

PCI_* signals setup time

1.2

PCI_* signals hold time

0.5

LIO_* signals setup time

1.2

LIO_* signals hold time

0.5

DDR2_DQ*/CB* signals setup time

0.1

DDR2_DQ*/CB* signals hold time

0.175

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