STLS2F02 datasheet(17/49 Pages) STMICROELECTRONICS

17 / 49 page

STLS2F02

IO bus interface description

17/49

IO bus interface description

The STLS2F02 processor IO interface consists of the PCI bus and a local bus. The PCI bus

is used to for generic peripheral device interface, while the local bus a simple interface for

processor boot or debug.

3.1

PCI interface characteristic

The PCI interface features are as follows:

●

PCI 2.3 and PCIX 1.0 compatible

●

Support PCI 66 MHz and PCIX133 MHz

●

Support dual address cycle for 64-bit addressing

●

Support 8 outstanding master request in PCIX mode

●

Support 4 delay-split read request in PCIX mode

3.2

Host and agent mode

The STLS2F02 PCI interface can work in host mode or agent mode, depending on the initial

value of signal PCI_CONFIG.

When the processor works in host mode, the interface initializes the bus device according to

the value of PCI_CONFIG[6:4]. In this case, PCI_IDSEL can be connected directly to GND.

When the processor works in agent mode, the initial value of the PCI bus defines the

working-mode of the interface. In host mode, on the system main board, the value of

PCI_CONFIG[6:4] should be set according to the ability of bus device. (Refer also to the

PCIX 1.0 standard)

3.3

PCI bus arbitrator

The PCI/PCIX bus arbitrator built into the STLS2F02 supports up t o 7 external masters. The

arbitration rules are two-level round robin scheduling. The level of each request is

determined by software configuration. The bus is granted to insert a dummy cycle during

switching. Bus parking can be configured as the last master or any specified master.

The internal request/grant wire of the interface can be set to connect to the number 0

request/grant wire by PCI_CONFIG [1] so that the external bus arbitrator can be used.

3.4

System interface connection

The STLS2F02 processor can be easily implemented in uniprocessor system. Since no

multi-processor cache coherence protocol is supported in the PCI interface, the cache

coherence should be managed by software in a multiprocessor system.

STLS2F02 데이터시트(PDF) 17 Page - STMicroelectronics

STLS2F02 데이터시트(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

데이터시트 다운로드

링크 URL