STLS2F02 datasheet(23/49 Pages) STMICROELECTRONICS

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STLS2F02

DDR2 SDRAM controller interface description

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4.3

DDR2 SDRAM write protocol

As shown in Figure 9 DDR2 SDRAM write protocol, the command (CMD) includes RAS_n,

CAS_n and WE_n. When a write request happens, RAS_n=1, CAS_n=0,and WE_n=0.

Unlike a read transaction, DQM is used to identify the write mask. In other words, the

number of written bytes is needed. DQM is synchronous with DQS.

Figure 9.

DDR2 SDRAM write protocol

CAS latency = 3, write latency = read latency = 2, burst length = 4

4.4

DDR2 SDRAM parameters

Since different DDR2 SDRAMs may be used in a system, DDR2 SDRAM needs

configuration after power-on reset. The JESD79-2B standard defines the configuration

operations and procedure in detail. DDR2 is not available before the memory is initialized. In

STLS2F02-based systems, after the system motherboard is initialized, the DDR2 SDRAM

controller must configure the memory type before the memory is used. The configuration

parameters are written into the 29 64-bit registers corresponding to the physical address

0x0000 0000 0FFF FE00. In one register, single, multiple or partial parameter data can be

included. The configuration register and its parameters are shown in Table 12: DDR SDRAM

configuration parameter register format

Note:

Unused bits are reserved.

4.4.1

Memory initialization sequence

The memory initialization sequence is as follows:

System reset, aresetn signal is set to 0, all register content is set to its initial value

System reset release, aresetn signal is set to 1

Issue 64-bit write command to configuration register, all 29 registers are configured. If

Issue 64-bit write command to register CTRL_03. Set the parameter of start to 1. The

memory controller then sends the initial instruction to memory automatically.

CMD

WRITE A

NOP

Precharge

NOP

Bank A

Activate

≤ tDQS6

WL = RL - 1 = 2

DINA0

DINA1

DINA2

DINA3

CK/CK

DQS/DQS

DQS

≥ WR

≥ tRP

Completion of

the Burst Write

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