| 전자부품 데이터시트 검색엔진 |
|
H838532H 데이터시트(PDF) 90 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H838532H 데이터시트(HTML) 90 Page - Renesas Technology Corp |
|
90 / 508 page ![]() Section 3 Exception Handling Rev. 1.00 May 30, 2008 Page 70 of 484 REJ09B0436-0100 Bit 6: A/D converter interrupt request flag (IRRAD) Bit 6 IRRAD Description 0 Clearing condition: (initial value) When IRRAD = 1, it is cleared by writing 0 1 Setting condition: When A/D conversion is completed and ADSF is cleared to 0 in ADSR Bit 5: Reserved bit Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset. Bit 4: Timer G interrupt request flag (IRRTG) Bit 4 IRRTG Description 0 Clearing condition: (initial value) When IRRTG = 1, it is cleared by writing 0 1 Setting condition: When the TMIG pin is designated for TMIG input and the designated signal edge is input, or when TCG overflows while OVIE is set to 1 in TMG Bit 3: Timer FH interrupt request flag (IRRTFH) Bit 3 IRRTFH Description 0 Clearing condition: (initial value) When IRRTFH = 1, it is cleared by writing 0 1 Setting condition: When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH) match in 16-bit timer mode |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |